DSP implementation of Turbo codes using the soft output Viterbi algorithm

There are various algorithms used for the iterative decoding of two-dimensional systematic convolutional codes in applications such as spread-spectrum communications and CDMA detection. The main objective of these decoding schemes is to approach the Shannon limit in signal-to-noise ratio while keeping the system complexity and processing delay to a minimum. One such scheme proposed recently is termed Turbo (de)coding. Through the use of Log-likelihood algebra, it is shown that a decoder can be developed which accepts soft inputs as a priori information and delivers soft outputs consisting of channel information, a priori information and extrinsic information to subsequent stages of iteration. The output is then used as the a priori input information for the next iteration. Realization of the Turbo decoder is performed on the digital signal processing chip, TMS320C30 by Texas Instruments using a low complexity soft-input soft-output decoding algorithm. Hardware issues such as memory and processing time are addressed and how they are impacted by the chosen decoding scheme. Test results of the BER performance are presented for various block sizes and number of iterations.