Finite element modeling of dislocation multiplication in microelectronic and optoelectronic devices/circuits

Two-dimensional and three-dimensional methodologies are developed to determine the dislocation multiplication in microelectronic and optoelectronic devices/circuits. A two-dimensional finite element code is developed to simulate the dislocation multiplication in microelectronic and optoelectronic devices/circuits. Example two-dimensional analyses are performed and analysis results are presented. The three-dimensional methodology is successfully implemented using ANSYS APDL Language within the ANSYS program. A three dimensional heterojunction bipolar transistor model is generated. CFD-thermal and structural analyses are performed to determine temperature fields and dislocation densities, which are calculated as functions of time, thickness of the thermal shunt, and heat generation rates.