Microprocessor design for non-discretionary multilevel security

Microprocessor design for data security is examined with regard to both methodology and implementation. The examination begins with seven commercial 32-bit microprocessors which are evaluated against a set of previously published requirements for secure hardware. Then, the methodology and implementation of data secure microprocessor design is presented using an original design. The presentation includes a description of the security policy implemented, a model of secure operation, and a detailed description of the design. The security-related overhead of the new design is compared to that of two commercial microprocessors. The design is then validated with a formal proof. Finally, the design is shown to protect against several generic attacks.