Modeling multiple abstraction levels in SoC using SystemC

Technological advances are providing us with the capability to integrate more and more functionality into a single chip. This is leading to a new design paradigm, System On a Chip (SoC). SoC design brings with it new challenges and difficulties. Managing these challenges and complexity necessitate modeling of systems at a hierarchy of abstraction levels starting from System Level down to Register Transfer Level. Using a single language across all these levels would ensure that the models are consistent and error-free. SystemC is one such language that has the infrastructure for specifying the design at System level, Behavioral level and RT levels of abstraction. This thesis showcases the same using two design examples---Simplex Data Protocol and General Purpose Timer (GPT) peripheral. Coding style and level of detailing at different levels are shows. Process of refining from one level to another is illustrated. GPT peripheral module designed in this thesis work can be further reused as a timer library component in system architectures.