Performance analysis of a very fast packet switching system for broadband ISDN

Rapid advances in technology have resulted in the evolution of Integrated Services Digital
Networks (ISDNs) to Broadband ISDNs (BISDNs). This thesis discusses and evaluates the
performance of a high speed and high capacity packet switching system architecture for
BISDNs. This system supports various high speed communication services like data, voice,
and video services. The main performance criterion is the mean switching delay, which
is defined as the packet transfer delay through the bus and through the loop connecting
various switch modules in the system. Other performance criteria are power and system
throughput. The performance parameters are evaluated separately for both data and control
(signaling) packets. The effects of the number of switch modules in the system, the data
packet length, and the ratio of arrival rate of data to control packets are examined.
It is observed that the switching delay and throughput increase with an increase in the
traffic intensity for any number of switching modules and the ratio of arrival rate of data
to control packets. The delay for data packets is found to be higher for lower values of
this ratio and vice versa. The power is found to be maximum for about 70% load. The
switching delay in this simulation model is found to be less than one millisecond for data
packets.