Computer architecture

A cross-layer design architecture featuring a new network
stack component called a controller is presented. The
controller takes system status information from the protocol
components and uses it to tune the behavior of the network
stack to a given performance objective. A controller design
strategy using a machine learning algorithm and a simulator
is proposed, implemented, and tested. Results show the
architecture and design strategy are capable of producing a
network stack that outperforms the existing protocol stack for
arbitrary performance objectives. The techniques presented
give network designers the flexibility to easily tune the
performance of their networks to suit their application. This
cognitive networking architecture has great potential for high
performance in future wireless networks.

Enhanced system design productivity is key to satisfying time-to-market demands. One
will have to exploit design reuse methodology to meet project schedule requirements.
Integration of components often fails due to various concurrency violations.
Concurrency issues arise when components executing in parallel share resources and
interact with each other. Such a system may have intermittent, yet catastrophic failures,
if these concurrency issues are not addressed properly. In this thesis, we propose a
methodology for developing concurrency compliant components from a requirement
document. We have applied this methodology for developing process management and
memory management aspects of a Real Time Operating System (RTOS). In this
methodology, we start from a "customer' s" requirement document that is then mapped to
activity diagram, swimlane diagram, class diagrams, and use case diagrams. To evolve a
concurrency compliant design, we use the Message Sequence Chart plug-in for the
Labeled Transition State Analyzer (LTSA). This plug-in lets us use Message Sequence
Charts rather than coding in Finite State Processes (FSP). Later, we use MLDesigner to
simulate our R TOS sub-system and demonstrate proper behavior of this sub-system.

Network architectures are described by the International Standard for
Organization (ISO), which contains seven layers. The internet uses four of these layers,
of which three are of interest to us. These layers are Internet Protocol (IP) or Network
Layer, Transport Layer and Application Layer. We need to protect against attacks that
may come through any of these layers. In the world of network security, systems are plagued by various attacks, internal and external, and could result in Denial of Service (DoS) and/or other damaging effects. Such attacks and loss of service can be devastating for the users of the system. The implementation of security devices such as Firewalls and Intrusion Detection Systems
(IDS), the protection of network traffic with Virtual Private Networks (VPNs), and the
use of secure protocols for the layers are important to enhance the security at each of
these layers.We have done a survey of the existing network security patterns and we have written the missing patterns. We have developed security patterns for abstract IDS, Behavior–based IDS and Rule-based IDS and as well as for Internet Protocol Security (IPSec) and Transport Layer Security (TLS) protocols. We have also identified the need for a VPN pattern and have developed security patterns for abstract VPN, an IPSec VPN and a TLS VPN. We also evaluated these patterns with respect to some aspects to simplify their application by system designers. We have tried to unify the security of the network layers using security patterns by tying in security patterns for network transmission, network protocols and network boundary devices.

We propose a new minimum total communication distance (TCD) algorithm and an optimal TCD algorithm for broadcast in a 2-dimensional mesh (2-D mesh). The former generates a minimum TCD from a given source node, and the latter guarantees a minimum TCD among all the possible source nodes. These algorithms are based on a divide-and-conquer approach where a 2-D mesh is partitioned into four submeshes of equal size. The source node sends the broadcast message to a special node called an eye in each submesh. The above procedure is then recursively applied in each submesh. These algorithms are extended to a 3-dimensional mesh (3-D mesh), and are generalized to a d-dimensional mesh or torus. In addition, the proposed approach can potentially be used to solve optimization problems in other collective communication operations.

The techniques employed in integrated circuit (IC) design have advanced significantly in the past decade. Design automation tools now offer hardware description languages (HDLs) for modeling and testing new designs. Some tools can even synthesize an IC from a model written in an HDL. Such design tools promise to facilitate greatly the development of new IC designs. They also make it possible for engineering students to learn advanced techniques of IC design and computer architecture in a classroom setting. Two examples of such state-of-the-art design tools are Design Framework and Epoch. In this work, we present a hierarchical design for a reduced-instruction-set computer (RISC) processor, which we implemented using Design Framework and Epoch. The processor is based on the DLX architecture proposed by Hennessy and Patterson. We implemented our design according to a top-down methodology, which worked very well in these design tools.

The primary emphasis of this thesis is to study the behavioral characteristics of Fiber Distributed Data Interface (FDDI) and Distributed Queue Dual Bus (DQDB) High Speed Local Area Networks (HSLANs). An FDDI architecture with passive interfaces is proposed to provide a reliable and efficient network topology. This network architecture outperforms the existing FDDI architecture with active interfaces in terms of small asynchronous packet delays and high asynchronous packet throughput. The design and implementation issues involved in the design of the hierarchical (multi-level) DQDB and FDDI networks are also presented. The hierarchical network architecture provides modularity and scalability with respect to speed and the number of users. Simulation models are developed for each of these network architectures to study their performance. Simulation results are presented in terms of medium access delay, throughput, and packet delays.

Multiprocessor systems have demonstrated great potential for meeting the ever increasing demand for higher performance. In this thesis, we develop simulation models with fewer and more realistic assumptions to evaluate the performance of the circuit-switched cluster-based multiprocessor system. We then introduce a packet-switched variation of the cluster-based architecture and develop simulation models to evaluate its performance. The analysis of the cluster-based systems is performed for both uniform and non-uniform memory reference models. We conducted similar analysis for the crossbar and multiple-bus systems. Finally, the results of the cluster-based systems are compared to those obtained for the crossbar and the multiple-bus systems.

In this thesis, processor allocation in hypercube computers is viewed to consist of the following three components. The ability to have complete subcube recognition, the heuristics and methods to speedup the recognition of free subcubes, and the policy to schedule incoming tasks to reduce the fragmentation of the hypercube. We propose a fast processor allocation strategy for hypercube computers called modified gray code (MGC). The MGC strategy achieves full subcube recognition with much less complexity than the multiple gray code and the tree collapse strategies. It is the first bitmapped strategy to incorporate binary search and heuristics to locate free subcubes, and has a new scheduling policy which significantly reduces the fragmentation of the hypercube. Simulation programs have been developed to compare the performance of the MGC to that of the other strategies so as to demonstrate its effectiveness. Results obtained showed that, in most of the situations, the MGC outperformed the other strategies, especially when the system load is high. We have also investigated processor allocation methods for real-time systems with fault-tolerant considerations. We propose methods that can handle a minimum of two dynamically occurring faults, without slowdown in execution and with a constant slowdown in communication of 3.

Interprocessor communication plays an important role in the performance of multicomputer systems, such as hypercube multicomputers. In this thesis, we consider the multicast problem for a hypercube system in the presence of faulty components. Two types of algorithms are proposed. Type 1 algorithms, which are developed based on local network information, can tolerate both node failures and link failures. Type 2 algorithms, which are developed based on limited global network information, ensure that each destination receives message through the shortest path. Simulation results show that type 2 algorithms achieve very good results on both time and traffic steps, two main criteria in measuring the performance of interprocessor communication.

Research is under way to fabricate large-area thin-film transistor arrays produced on a thin polyimide substrate. The polyimide substrate is available in long thirty centimeter wide rolls of tape, and lithography hardware is being developed to expose hundreds of meters of this tape with electrically addressable light modulators which can resolve 2 $\mu$m features. A fault-tolerant memory architecture is proposed that is capable of storing one hour of D-1 component digital video (almost 10^12 bits) in real-time, on eight two-hundred meter long tapes. Appropriate error correcting codes and error concealment are proposed to compensate for drop-outs resulting from manufacturing defects so as to yield video images with error rates low enough to survive several generations of copies.