Computer architecture

The rapid evolution of silicon technology has brought exponential benefits in cost, scale of integration, power per function, size per function and speed. The ability to place multiple function "systems" on a single silicon chip, reduce development cycle while increasing product functionality, performance and quality. With this increased complexity, ability to model at high level of abstraction becomes crucial. Also, the fact that no known existing complete system on chip design packages with perfect tools, models, and formalisms further slows down and complicates the development. This dissertation provides an integrated environment for hardware software co-design at a high level of abstraction. We have developed a SystemC based cockpit for this purpose. The cockpit, known as SHINE consists of many components including architectural components, operating system components, and application software components. The ability to represent and manipulate these components at high levels of abstraction is a major challenge. To address these challenges we have developed a set of principles. Important principles evolved are synergy of separation of concerns, reusability, flexibility, ease of use, and support for multiple levels of abstraction. 'Synergy of Separation of Concerns' helps in maintaining transparency during all instances in the development of the integrated environment. One application is transparent to another application and in turn to the system architecture. Also in the system architecture, each module is designed independent of other modules. Well defined interfaces enable this transparency and easier to integrate. This also enhances component reuse and overall design environment modularity. 'Ease of Use' allows the user to shorten the learning curve involved. In SHINE, 'Flexibility' is addressed via support for plug-and-play of components in the design environment. We provide results to show the implementation of these principles. SHINE provides a cost-effective mechanism to develop a system co-design infrastructure. This will lead to early system verification and performance estimation resulting in shorter time-to-market. The design flow developed is structured and is easily extended. This is an exploratory study that is the result of a long term industrial collaboration to enhance design productivity. Significantly more work lies ahead in developing an industry standard tool and methodology.

The increasing system design complexity is negatively impacting the overall system design productivity by increasing the cost and time of product development. One key to overcoming these challenges is exploiting Component Based Engineering practices. However it is a challenge to select an optimum component from a component library that will satisfy all system functional and non-functional requirements, due to varying performance parameters and quality of service requirements. In this thesis we propose an integrated framework for component selection. The framework is a two phase approach that includes a system modeling and analysis phase and a component selection phase. Three component selection algorithms have been implemented for selecting components for a Network on Chip architecture. Two algorithms are based on a standard greedy method, with one being enhanced to produce more intelligent behavior. The third algorithm is based on simulated annealing. Further, a prototype was developed to evaluate the proposed framework and compare the performance of all the algorithms.

Cache memory is used, in most single-core and multi-core processors, to improve performance by bridging the speed gap between the main memory and CPU. Even though cache increases performance, it poses some serious challenges for embedded systems running real-time applications. Cache introduces execution time unpredictability due to its adaptive and dynamic nature and cache consumes vast amount of power to be operated. Energy requirement and execution time predictability are crucial for the success of real-time embedded systems. Various cache optimization schemes have been proposed to address the performance, power consumption, and predictability issues. However, currently available solutions are not adequate for real-time embedded systems as they do not address the performance, power consumption, and execution time predictability issues at the same time. Moreover, existing solutions are not suitable for dealing with multi-core architecture issues. In this dissertation, we develop a methodology through cache optimization for real-time embedded systems that can be used to analyze and improve execution time predictability and performance/power ratio at the same time. This methodology is effective for both single-core and multi-core systems. First, we develop a cache modeling and optimization technique for single-core systems to improve performance. Then, we develop a cache modeling and optimization technique for multi-core systems to improve performance/power ratio. We develop a cache locking scheme to improve execution time predictability for real-time systems. We introduce Miss Table (MT) based cache locking scheme with victim cache (VC) to improve predictability and performance/power ratio. MT holds information about memory blocks, which may cause more misses if not locked, to improve cache locking performance.

Multiple threads can run concurrently on multiple cores in a multicore system and improve performance/power ratio. However, effective core allocation in multicore and manycore systems is very challenging. In this thesis, we propose an effective and scalable core allocation strategy for multicore systems to achieve optimal core utilization by reducing both internal and external fragmentations. Our proposed strategy helps evenly spreading the servicing cores on the chip to facilitate better heat dissipation. We introduce a multi-stage power management scheme to reduce the total power consumption by managing the power states of the cores. We simulate three multicore systems, with 16, 32, and 64 cores, respectively, using synthetic workload. Experimental results show that our proposed strategy performs better than Square-shaped, Rectangle-shaped, L-Shaped, and Hybrid (contiguous and non-contiguous) schemes in multicore systems in terms of fragmentation and completion time. Among these strategies, our strategy provides a better heat dissipation mechanism.

In this thesis, a framework for improving model-driven system design productivity with Requirements-Driven Design Automation (RDDA) is presented. The key to the proposed approach is to close the semantic gap between requirements, components and architecture by using compatible semantic models for describing product requirements and component capabilities, including constraints. An ontology-based representation language is designed that spans requirements for the application domain, the software design domain and the component domain. Design automation is supported for architecture development by machine-based mapping of desired product/subsystem features and capabilities to library components and by synthesis and maintenance of Systems Modeling Language (SysML) design structure diagrams. The RDDA framework uses standards-based semantic web technologies and can be integrated with exiting modeling tools. Requirements specification is a major component of the system development cycle. Mistakes and omissions in requirements documents lead to ambiguous or wrong interpretation by engineers, causing errors that trickle down in design and implementation with consequences on the overall development cost. We describe a methodology for requirements specification that aims to alleviate the above issues and that produces models for functional requirements that can be automatically validated for completeness and consistency. The RDDA framework uses an ontology-based language for semantic description of functional product requirements, SysML structure diagrams, component constraints, and Quality of Service. The front-end method for requirements specification is the SysML editor in Rhapsody. A requirements model in Web Ontology Language (OWL) is converted from SysML to Extensible Markup Language Metadata Interchange (XMI) representation.