Multiprocessors

Recent advances in computer technology have increased the performance of computers, but application requirements will always exceed the performance level available today. This requires the use of multiprocessors. The importance of multiprocessor systems is increasing due to many reasons, one of which is reliability. Reliability is also an important aspect in any computer system design. For reliable operation the system should be able to detect and locate most of its faults. The idea of using a set of processes collectively known as a Recovery Metaprogram (RMP) is applied in this thesis to system diagnosis. Several error location algorithms are analyzed and compared. Most of them are comparison methods. A new algorithm, called Duplication algorithm, is developed and analyzed. Primitives, oriented to the specific functions of error diagnosis, required by the RMP to coordinate recovery functions are also developed in this thesis.

Concurrency at both the hardware and software level has recently been
considered as the solution to the classic Von Neuman bottleneck in
system design. Introduced by Inmos, the Occam language and the
Transputer microprocessor provide simple and elegant building blocks
for a concurrent system. This thesis proposes a set of algorithms to
find an optimal deterministic schedule for an Occam program executed on
a network of Transputers. Also discussed are features of the network
relevant to the problem of scheduling, and a complete example is
provided to illustrate the scheduler. The approaches described can be
used as a basis for implementing a flexible general purpose multiprocessor
system.

We explored the portability of various OS concepts to silicon. We wish to develop intellectual property blocks of various OS concepts, so that an embedded system designer has the option to mix and match. As a first step we have looked at inter-process communication (IPC) and Process Scheduling. We have implemented simple hardware building blocks for these. In our problem we utilize two processors, one each assigned as Master and Slave. Master is in control and implements the OS algorithms, while the Slave executes the user/application code. We show that these OS building blocks can be implemented in the hardware. Future effort of our group is to build a portfolio of OS IP blocks and explore optimization for various applications.

Providing multiprocessor capability to the class of computers commonly referred to as personal workstations is the next evolutionary step in their development. Uniprocessor workstations limit the user in throughput, reliability, functionality, and architecture. Multiprocessor workstations have the potential of increasing system throughput. A multiprocessor system with expanded architecture derived from a set of heterogeneous processors gives the user a diverse application base within a single system. The replication and diversity offered in systems of this design, when coupled with fault-tolerant design techniques, enhances system reliability. A heterogeneous multiprocessor architecture is presented which combines loosely- and tightly-coupled configurations (multicomputer and multiprocessor). This architecture provides for incremental growth of the system, either by static or dynamic reconfiguration. The software view of the system is that of an object-oriented environment. The object-oriented approach is used to unify the heterogeneous nature of the system. The process is the unit of concurrency in the system and cooperating concurrent processes are supported. A set of system primitives are provided to support the requirements of a heterogeneous multiprocessing environment. A virtual machine layer controls the distribution of processes and allocation of resources in the system. A virtual network is used to provide communication paths and resource sharing. The virtual network is designed to be bridged to an external physical network. The system requirements for a secure and reliable operating environment are incorporated into the design. This system utilizes "hardware porting" as a means to overcome the lag of software support for hardware advances. Rather than software port an entire application base to a new system architecture, hardware porting brings the required instruction set architecture to the applications. This heterogeneous multiprocessor architecture builds on a popular system architecture, the scIBM PS/2 with the Micro Channel system bus. Incorporating a second bus, the scSCSI bus, as a system extension is explored.

The rapid evolution of silicon technology has brought exponential benefits in cost, scale of integration, power per function, size per function and speed. The ability to place multiple function "systems" on a single silicon chip, reduce development cycle while increasing product functionality, performance and quality. With this increased complexity, ability to model at high level of abstraction becomes crucial. Also, the fact that no known existing complete system on chip design packages with perfect tools, models, and formalisms further slows down and complicates the development. This dissertation provides an integrated environment for hardware software co-design at a high level of abstraction. We have developed a SystemC based cockpit for this purpose. The cockpit, known as SHINE consists of many components including architectural components, operating system components, and application software components. The ability to represent and manipulate these components at high levels of abstraction is a major challenge. To address these challenges we have developed a set of principles. Important principles evolved are synergy of separation of concerns, reusability, flexibility, ease of use, and support for multiple levels of abstraction. 'Synergy of Separation of Concerns' helps in maintaining transparency during all instances in the development of the integrated environment. One application is transparent to another application and in turn to the system architecture. Also in the system architecture, each module is designed independent of other modules. Well defined interfaces enable this transparency and easier to integrate. This also enhances component reuse and overall design environment modularity. 'Ease of Use' allows the user to shorten the learning curve involved. In SHINE, 'Flexibility' is addressed via support for plug-and-play of components in the design environment. We provide results to show the implementation of these principles. SHINE provides a cost-effective mechanism to develop a system co-design infrastructure. This will lead to early system verification and performance estimation resulting in shorter time-to-market. The design flow developed is structured and is easily extended. This is an exploratory study that is the result of a long term industrial collaboration to enhance design productivity. Significantly more work lies ahead in developing an industry standard tool and methodology.