Multipliers (Mathematical analysis)

High speed low power scalable multiplier is needed in computation intensive DSP applications such as video and image compression algorithms. We used an algorithm that folds the larger bit-width operands so smaller bit-width multipliers can be used. Successive folding on operands can be done until a desired threshold is reached. This method has inherent advantages of reuse of optimized building blocks, dynamic reconfiguration, and low power. We implemented a hardware multiplier based on this algorithm using Verilog hardware description language. Our results show that this multiplier exhibited significant power advantage over Array and Wallace Tree multipliers for comparable speeds, but had higher gate counts.

Identifying and classifying the complemented subspaces of L p , p > 2, has provided much insight into the geometric structure of Lp . In 1981, Bourgain, Rosenthal, and Schechtman proved the existence of uncountably many isomorphically distinct complemented subspaces of L p , p > 2. In 1999, Dale Alspach introduced a systematic method of studying the complemented subspaces of Lp , p > 2. In this thesis, the theory of Lp spaces is developed with a concentration on techniques used to study the complemented subspaces. We define the Alspach norm and show that the possible complemented subspaces of Lp , p > 2, generated by two compatible partitions and weights are £2, £p, £2 EB £p, and(2.:EfJ £2)ep ' We have not discovered any previously unknown complemented subspaces of Lp , but this method has reduced the study and classification of these subspaces to a study of partitions of N.