Electric filters, Digital--Computer programs

In this thesis, a partial fraction expansion of a separable-in-denominator 2-D transfer function is given. Based on this expansion, several novel realizations of separable-in-denominator 2-D filter are provide. These realizations have the properties of highly parallel structure and improved throughput delay. The performance figures are given in the tables. A method of evaluation of quantization error of separable-in-denominator 2-D filter is also derived by using the residue method. Formulas for calculation of roundoff noise of proposed structures are provided. Two programs which can be used to calculate the roundoff noise of proposed structure are listed in the Appendix. To run the programs, we need only to input the constant coefficients of expanded transfer function. At last, an optimal block realization of separable-in-denominator 2-D filter is discussed and the criterion for the absence of limit cycles for a second-order 2-D block is given.

A PCM MF Receiver based on either analog or digital filters
results in a fairly large chip. A recent publication attempts to
address this issue by using certain approximations that replace
multiplications with simple additions and subtractions. This results
in a significantly smaller chip. In our research, we have further
refined/changed the algorithms and approximations in order to reduce
the chip size further and the chip count to one.
A simulation model corresponding to this, written in ISPS and
Fortran, was extensively utilized to verify that the proposed
receiver would meet and/or exceed all the commercial specifications.
Subsequent to that, we initiated hardware design using structured
methodologies. Hardware modules written in a high-level hardware
description language have been simulated for functional validity. We
expect to utilize mixed mode simulations and hierarchical design
concepts in translating this high-level description to a hardware
implementation on a semi-custom CMOS chip.