Telephone

A PCM MF Receiver based on either analog or digital filters
results in a fairly large chip. A recent publication attempts to
address this issue by using certain approximations that replace
multiplications with simple additions and subtractions. This results
in a significantly smaller chip. In our research, we have further
refined/changed the algorithms and approximations in order to reduce
the chip size further and the chip count to one.
A simulation model corresponding to this, written in ISPS and
Fortran, was extensively utilized to verify that the proposed
receiver would meet and/or exceed all the commercial specifications.
Subsequent to that, we initiated hardware design using structured
methodologies. Hardware modules written in a high-level hardware
description language have been simulated for functional validity. We
expect to utilize mixed mode simulations and hierarchical design
concepts in translating this high-level description to a hardware
implementation on a semi-custom CMOS chip.