Model
Digital Document
Publisher
Florida Atlantic University
Description
With the increasing complexity of the system design, it has become very critical to
enhance system design productivity to meet with the time-to-market demands. Real Time
embedded system designers are facing extreme challenges in underlying architectural
design selection. It involves the selection of a programmable, concurrent, heterogeneous
multiprocessor architecture platform. Such a multiprocessor system on chip (MPSoC)
platform has set new innovative trends for the real-time systems and system on Chip
(SoC) designers. The consequences of this trend imply the shift in concern from
computation and sequential algorithms to modeling concurrency, synchronization and
communication in every aspect of hardware and software co-design and development.
Some of the main problems in the current deep sub-micron technologies characterized by
gate lengths in the range of 60-90 nm arise from non scalable wire delays, errors in signal
integrity and un-synchronized communication. These problems have been addressed by
the use of packet switched Network on Chip (NOC) architecture for future SoCs and
thus, real-time systems. Such a NOC based system should be able to support different levels of quality of service (QoS) to meet the real time systems requirements. It will
further help in enhancing the system productivity by providing a reusable communication
backbone. Thus, it becomes extremely critical to properly design a communication
backbone (CommB) for NOC. Along with offering different levels of QoS, CommB is
responsible directing the flow of data from one node to another node through routers,
allocators, switches, queues and links. In this dissertation I present a reusable component
based, design of CommB, suitable for embedded applications, which supports three types
of QoS (real-time, multi-media and control applications).
enhance system design productivity to meet with the time-to-market demands. Real Time
embedded system designers are facing extreme challenges in underlying architectural
design selection. It involves the selection of a programmable, concurrent, heterogeneous
multiprocessor architecture platform. Such a multiprocessor system on chip (MPSoC)
platform has set new innovative trends for the real-time systems and system on Chip
(SoC) designers. The consequences of this trend imply the shift in concern from
computation and sequential algorithms to modeling concurrency, synchronization and
communication in every aspect of hardware and software co-design and development.
Some of the main problems in the current deep sub-micron technologies characterized by
gate lengths in the range of 60-90 nm arise from non scalable wire delays, errors in signal
integrity and un-synchronized communication. These problems have been addressed by
the use of packet switched Network on Chip (NOC) architecture for future SoCs and
thus, real-time systems. Such a NOC based system should be able to support different levels of quality of service (QoS) to meet the real time systems requirements. It will
further help in enhancing the system productivity by providing a reusable communication
backbone. Thus, it becomes extremely critical to properly design a communication
backbone (CommB) for NOC. Along with offering different levels of QoS, CommB is
responsible directing the flow of data from one node to another node through routers,
allocators, switches, queues and links. In this dissertation I present a reusable component
based, design of CommB, suitable for embedded applications, which supports three types
of QoS (real-time, multi-media and control applications).
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