Agarwal, Ankur

The Smart Campus project envisions a university campus where technology assists
faculty, staff, students and visitors to improve and more efficiently accomplish their daily
activities. The objective of this project is to develop a smart phone application that assists
users in finding a certain location on campus, locating their friends and professors,
interacting with any student or professors of the campus, get the count of users at certain
locations and remain updated about all the events and campus news. Through this project,
an idea of ‘Futuristic Social Network’ in a Campus is modeled and developed on Android
platform.

In recent years there has been dramatic growth in mobile devices and
technologies. According to reports from comScore [1], 47% users in the United States
(aged more than 13) are using a smartphones as their primary phone. Smartphone offers
more advanced computing ability and connectivity than contemporary phones. In today’s
world, a user wants to keep their smartphones private, because of the personal
information present in it. Among these users, some of them are minors. This thesis
addresses the functionality to track/control the mobile activities of minors by their parents
using mobile phones. As a parent they want to know, whom his/her child is talking to and
for what they are accessing browser for. Cellular network companies are providing
number blocking services from the carrier side, but those are monthly paid services. In this thesis, we propose application architecture for remotely control the child phone
and grant access to selected numbers for call and text. We use the emerging Android mobile platform and Google nexus phones to implement and test the application. This architecture will help developers to make more innovative applications in future which helps parent to access child phone information. We performed a study and reported the result using the proposal.

There is a mushrooming demand for battery operated applications that require intensive computation in portable environments. This has motivated the research and development of techniques that reduce power in CMOS digital circuits while maintaining their computational throughput. The two essentials to achieve a low power design are miniaturization and long battery life. Lowering the supply voltage is one of the most effective ways to achieve low-power performance as power dissipation in digital CMOS circuits is approximately proportional to the square of supply voltage. The basic idea behind this thesis is that it proposes new designs of transfer gate based logical circuits, which use lower supply voltage and less number of transistors than the conventional designs. This work evaluates the obtained results from the proposed designs of the low-power ALU with that from the standard CMOS, other low power designs namely, Wang's XOR, XNOR and Inverter based gates. It was observed that the proposed designs perform better in terms of power consumption than the standard CMOS designs, and the other low power designs mentioned above.