System design

System modeling has the potential to enhance system design productivity by providing a
platform for system performance evaluations. This model must be designed at an abstract
level, hiding system details. However, it must represent any subsystem or its components
at any level of specification details. In order to model such a system, we will need to
combine various models-of-computation (MOC). MOC provide a framework to model
various algorithms and activities, while accounting for and exploiting concurrency and
synchronization aspects. Along with supporting various MOC, a modeling environment
should also support a well developed library. In this thesis, we have explored various
modeling environments. MLDesigner (MLD) is one such modeling environment that
supports a well developed library and integrates various MOC. We present an overview
and discuss the process of system modeling with MLD. We further present an abstract
model of a Network-on-Chip in MLD and show latency results for various customizable
parameters for this model.

In response to the massive amounts of data that make up a large number of bioinformatics datasets, it has become increasingly necessary for researchers to use computers to aid them in their endeavors. With difficulties such as high dimensionality, class imbalance, noisy data, and difficult to learn class boundaries, being present within the data, bioinformatics datasets are a challenge to work with. One potential source of assistance is the domain of data mining and machine learning, a field which focuses on working with these large amounts of data and develops techniques to discover new trends and patterns that are hidden within the data and to increases the capability of researchers and practitioners to work with this data. Within this domain there are techniques designed to eliminate irrelevant or redundant features, balance the membership of the classes, handle errors found in the data, and build predictive models for future data.

One of the main applications of machine learning in bioinformatics is the construction of classification models which can accurately classify new instances using information gained from previous instances. With the help of machine learning algorithms (such as supervised classification and gene selection) new meaningful knowledge can be extracted from bioinformatics datasets that can help in disease diagnosis and prognosis as well as in prescribing the right treatment for a disease. One particular challenge encountered when analyzing bioinformatics datasets is data noise, which refers to incorrect or missing values in datasets. Noise can be introduced as a result of experimental errors (e.g. faulty microarray chips, insufficient resolution, image corruption, and incorrect laboratory procedures), as well as other errors (errors
during data processing, transfer, and/or mining). A special type of data noise
called class noise, which occurs when an instance/example is mislabeled. Previous
research showed that class noise has a detrimental impact on machine learning algorithms (e.g. worsened classification performance and unstable feature selection). In
addition to data noise, gene expression datasets can suffer from the problems of high
dimensionality (a very large feature space) and class imbalance (unequal distribution
of instances between classes). As a result of these inherent problems, constructing accurate classification models becomes more challenging.

A comparative analysis of two methods of bus arbitration used by a
multiprocessing system with a single main bus is performed. The major
performance parameters are delay time and the average number of active
processors, called processing power. The bus arbitration methods are
described using state and timing diagrams. Multiprocessor systems using
these methods of arbitration are then modeled using Markov chains to
enable the formulation of processing power. From processing power
other performance parameters can be derived. A comparison is then made
among the two bus arbitration methods based on the analytical results
where processors access the bus at an equal rate. Simulations of
multiprocessor systems using either of the two arbitration methods were
performed to validate the analytical models for equal bus request rates.
Simulations are also performed of a system of processors using the main
bus at unequal rates.

With the increase in the applications of computer technology, there are more and more demands for the use of computer systems in the area of real-time applications and critical systems. Reliability and performance are fundamental design requirements for these applications. In this dissertation, we develop some specific aspects of a fault-tolerant decentralized system architecture. This system can execute concurrent processes and it is composed of processing elements that have only local memories with point-to-point communication. A model using hierarchical layers describes this system. Fault tolerance techniques are discussed for the applications, software, operating system, and hardware layers of the model. Scheduling of communicating tasks to increase performance is also addressed. Some special problems such as the Byzantine Generals problem are considered. We have shown that, by combining reliable techniques on different layers and with consideration of system performance, one can provide a system with a very high level reliability as well as performance.

In this study, a tool has been developed which traces the storage subsystem workload at the subsystem level. Due to hardware assistance, this tool has very little overhead. This is achieved by incorporating the tracing routine in the microcode of the IBM SCSI adapter. The I/O traces are collected, in realtime, on a PS/2 connected to the modified SCSI adapter via an asynchronous link. These traces are then processed and studied. We have developed a scheme to characterize the workload by studying the parameters of the traced workload. These parameters include LBA distributions, interarrival time distribution, size distributions, ratios between read requests and write requests, adapter's cache performance, etc. In this study, workload characterization of storage subsystems in OS/2, AIX and NetWare environments was performed. An algorithm for synthesizing of the workload was also developed and implemented as part of this study.

The project that was created for this thesis is a Case Based Reasoning application to be used in high level software design for Siemens' Telecommunications software. Currently, design engineers search for existing subtasks in the software that are similar to subtasks in their new designs by reading documentation and consulting with other engineers. The prototype for Software Design Using Case Based Reasoning (SDUCBR) stores these subtasks in a case library and enables the design engineer to locate relevant subtasks via three different indexing techniques. This thesis addresses knowledge representation and indexing mechanisms appropriate for this application. SDUCBR is domain-dependent. Cases are stored in a relational hierarchy to facilitate analyzing the existing implementation from various perspectives. The indexing mechanisms were designed to provide the software design engineer with the flexibility of describing a problem differently based on the objective, level of granularity, and special characteristics of the subtask.

Current multicore processors attempt to optimize consumer experience via task partitioning and concurrent execution of these (sub)tasks on the cores. Conversion of sequential code to parallel and concurrent code is neither easy, nor feasible with current methodologies. We have developed a mapping process that synergistically uses top-down and bottom-up methodologies. This process is amenable to automation. We use bottom-up analysis to determine decomposability and estimate computation and communication metrics. The outcome is a set of proposals for software decomposition. We then build abstract concurrent models that map these decomposed (abstract) software modules onto candidate multicore architectures; this resolves concurrency issues. We then perform a system level simulation to estimate concurrency gain and/or cost, and QOS (Qualify-of-Service) metrics. Different architectural combinations yield different QOS metrics; the requisite system architecture may then be chosen. We applied this 'middle-out' methodology to optimally map a digital camera application onto a processor with four cores.

Technological advances are providing us with the capability to integrate more and more functionality into a single chip. This is leading to a new design paradigm, System On a Chip (SoC). SoC design brings with it new challenges and difficulties. Managing these challenges and complexity necessitate modeling of systems at a hierarchy of abstraction levels starting from System Level down to Register Transfer Level. Using a single language across all these levels would ensure that the models are consistent and error-free. SystemC is one such language that has the infrastructure for specifying the design at System level, Behavioral level and RT levels of abstraction. This thesis showcases the same using two design examples---Simplex Data Protocol and General Purpose Timer (GPT) peripheral. Coding style and level of detailing at different levels are shows. Process of refining from one level to another is illustrated. GPT peripheral module designed in this thesis work can be further reused as a timer library component in system architectures.

Model reduction of large-scale systems over a specified frequency range of operation is studied in this research and reported in this dissertation. Frequency-domain balanced structures with integration of singular perturbation are proposed for model reduction of large-scale continuous-time as well as discrete-time systems. This method is applied to both open-loop as well as closed-loop systems. It is shown that the response of reduced systems closely resemble that of full order systems within a specified frequency range of operation. Simulation experiments for the model reduction of several large-scale, continuous and discrete-time systems demonstrate the superiority of the proposed technique over the previously available methods.