low power and high performance centralized full adder

In this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and verification of the proposed architecture and the standard full adder that were modeled with Verilog hardware description language. Lasi was used for the layout design of the proposed architecture and the standard full adder. After the layout, both the architectures were compiled separately using LASICKT and a corresponding .CIR file was generated. The .CIR file was imported and executed into WINSPICE3 for the simulation of the circuit.