Metal oxide semiconductors, Complementary

The research addressed and deliberated in this thesis refers to CMOS VLSI design approach of a Bluetooth™ receiver front-end. The performance outcome o f the design is verified with ADS™ RF simulation tool. Essentially the thesis offers an outline on the Bluetooth™ technology and its RF front-end component requirements. The relevant specifications of the
designed front-end blocks are identified and are in concurrence with CMOS technology based
topologies. For each block identified, both circuit parameters and device characteristics are chosen as
per available design formulations and empirical results in open literature. Specifically,
the topology sections designed include antenna input matching, transmit/receive switch,
necessary filters, low noise amplifier, mixer and phase lock loop units. The numerical
TM, (designed) circuit parameters are duly addressed in appropriate ADS simulation tools
and performance evaluations are conducted. Observed results including any deviations
are identified and reported. The thesis concludes with a summary and indicates direction
for future work.

There is a mushrooming demand for battery operated applications that require intensive computation in portable environments. This has motivated the research and development of techniques that reduce power in CMOS digital circuits while maintaining their computational throughput. The two essentials to achieve a low power design are miniaturization and long battery life. Lowering the supply voltage is one of the most effective ways to achieve low-power performance as power dissipation in digital CMOS circuits is approximately proportional to the square of supply voltage. The basic idea behind this thesis is that it proposes new designs of transfer gate based logical circuits, which use lower supply voltage and less number of transistors than the conventional designs. This work evaluates the obtained results from the proposed designs of the low-power ALU with that from the standard CMOS, other low power designs namely, Wang's XOR, XNOR and Inverter based gates. It was observed that the proposed designs perform better in terms of power consumption than the standard CMOS designs, and the other low power designs mentioned above.

We propose two approaches to design 1-bit full adders which can yield good performance at low power consumption. In the first approach, we design XOR/XNOR gates using a minimal number of CMOS transistors. Comparing with 10 different XOR/XNOR gates reported in literature, the new XOR/XNOR gates consume less power. The gates consisting of the smallest number of transistors are combined to create 1-bit full adders. The process is systematic and yields a total of 42 10-transistor full adders, 41 of which are new. Simulation results show that most of the new adders perform better than a previously existing 10-transistor adder and a complementary CMOS adder in terms of power and speed with heavier load. Three adders consistently perform better. In the second approach, we utilized a method called the centralized design to create four new 10-transistor full adders. Simulation results show that these new adders perform better than the previously existing 10-transistor and the complementary CMOS adder.

Implementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis algorithm and a new test generation approach, that are based on topologies rather than individual logic functions. We have found that 19 and 363 DCVS topologies can represent 256 and 65,536 functions, respectively, for the 3- and 4-varaible cases. Physical defect analysis was conducted with the aid of a building block approach to analyze the n-type logic tree and provides a basis for evolving hierarchical test pattern generation for the topologies.

In this thesis, we proposed a low power and high performance architecture for 1-bit full adder design. The proposed architecture was proven to offer a wide range of performance ability in terms of power consumption and speed. We implemented the architecture using a 2-input 2 multiplexers, an XOR and an XNOR gate. The proposed architecture and the Standard full adder were designed and simulated using Lasi, Winspice and Silos. Silos, a logic simulation environment was used in the design and verification of the proposed architecture and the standard full adder that were modeled with Verilog hardware description language. Lasi was used for the layout design of the proposed architecture and the standard full adder. After the layout, both the architectures were compiled separately using LASICKT and a corresponding .CIR file was generated. The .CIR file was imported and executed into WINSPICE3 for the simulation of the circuit.

We propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass-gates, five new high-performance full adder cells are obtained. Those new adder cells are tested along with the conventional 28-transistor CMOS adder cell. Testing results shows that the new adder cells have higher speed and lower power delay product values than the conventional 28-transistor CMOS adder cell.