Novel multiplexer-based architectures for full adder design

We propose five new Multiplexer-Based architectures for 1-bit full adder design. Using a 2-transistors multiplexer gate to implement the first architecture, we are able to produce a 12-transistor full adder cell, Comparing it to four different 10-transistors low-power full adder cells reported previously in literature, the new adder cell named MBA1-12T out performs all of them in power consumption and speed. By implementing those architectures using the 2-input CMOS multiplexer with pass-gates, five new high-performance full adder cells are obtained. Those new adder cells are tested along with the conventional 28-transistor CMOS adder cell. Testing results shows that the new adder cells have higher speed and lower power delay product values than the conventional 28-transistor CMOS adder cell.