Bisheh, Niasar Mojtaba

To address the increased interest in crypto hardware accelerators due to performance and efficiency concerns, implementing hardware architectures of different public-key cryptosystems has drawn growing attention. Pure hardware methodology enhances architecture’s performance over a hardware/software co-design scheme at the cost of a more extended design cycle, reducing the flexibility, and demands customized data paths for different protocol-level operations. However, using pure hardware architecture makes the design smaller, faster, and more efficient. This dissertation mainly focuses on designing crypto accelerators that can be used in embedded systems and Internet-of-Things (IoT) devices where performance and efficiency are critical as a hardware accelerator to offload computations from the microcontroller units (MCU). In particular, our objective is to create a system-on-chip (SoC) crypto-accelerator with an MCU that achieves high area-time efficiency. Our implementation can also be integrated as an off-chip solution; however, other criteria, such as performance, are often as important or more important than efficiency in the external crypto-chip design, which is beyond of this work. Not only does our architecture inherently provide protection against timing and simple power analysis (SPA) attacks, but also some advanced security mechanisms to avoid differential power analysis (DPA) attacks are included, which is missing in the literature. In a nutshell, the contributions are summarized as follows: