Public key cryptography

Cryptographic algorithms are being developed and incorporated into network security protocols to provide secure communication over vulnerable mediums like the Internet. These protocols utilize secret and public key mechanisms to carry out data integrity, confidentiality, authentication, and non-repudiation.
The urge to deploy cryptosystems on low-end devices, based on the constantly growing Internet of Things (IoT) world, requires optimal design and implementation of cryptographic algorithms and protocols to achieve small communicational and computational cost, while preserving the privacy of the transmitted data. Scenarios of low bandwidth, constrained memory, and limited processing power are common when targeting embedded devices; however, security requirements are still present due to the sensitive information that may be communicated. In this thesis, we address the need for optimal cryptographic primitives implementation design in terms of computing capabilities, energy and power consumption, and memory usage to accommodate the deployment of cryptographical systems on resource-constrained devices.

Euclidean lattices have attracted considerable research interest as they can be used to construct efficient cryptographic schemes that are believed to be quantum-resistant. The NTRU problem, introduced by J. Hoffstein, J. Pipher, and J. H. Silverman in 1996 [16], serves as an important average-case computational problem in lattice-based cryptography. Following their pioneer work, the NTRU assumption and its variants have been used widely in modern cryptographic constructions such as encryption, signature, etc.
Let Rq = Zq[x]/ (xn + 1) be a quotient polynomial ring. The standard NTRU problem asks to recover short polynomials f, g E Rq such that h - g/ f (mod q), given a public key h and the promise that such elements exist. In practice, the degree n is often a power of two. As a generalization of NTRU, the Module-NTRU problems were introduced by Cheon, Kim, Kim, and Son (IACR ePrint 2019/1468), and Chuengsatiansup, Prest, Stehle, Wallet, and Xagawa (ASIACCS '20).
In this thesis, we presented two post-quantum Digital Signature Schemes based on the Module-NTRU problem and its variants.

To address the increased interest in crypto hardware accelerators due to performance and efficiency concerns, implementing hardware architectures of different public-key cryptosystems has drawn growing attention. Pure hardware methodology enhances architecture’s performance over a hardware/software co-design scheme at the cost of a more extended design cycle, reducing the flexibility, and demands customized data paths for different protocol-level operations. However, using pure hardware architecture makes the design smaller, faster, and more efficient. This dissertation mainly focuses on designing crypto accelerators that can be used in embedded systems and Internet-of-Things (IoT) devices where performance and efficiency are critical as a hardware accelerator to offload computations from the microcontroller units (MCU). In particular, our objective is to create a system-on-chip (SoC) crypto-accelerator with an MCU that achieves high area-time efficiency. Our implementation can also be integrated as an off-chip solution; however, other criteria, such as performance, are often as important or more important than efficiency in the external crypto-chip design, which is beyond of this work. Not only does our architecture inherently provide protection against timing and simple power analysis (SPA) attacks, but also some advanced security mechanisms to avoid differential power analysis (DPA) attacks are included, which is missing in the literature. In a nutshell, the contributions are summarized as follows: