Phadnis, Mangirish Jayawant.

Optical Character Recognition systems have many applications in today's world of electronic computing. Various software implementations are currently being used. This thesis evolves a massively parallel hardware implementation for the system that is VLSI scaleable and may lead to substantial increase in the processing speed. This system involves various stages for preprocessing and processing of the image implemented with SIMD architecture, using simple processing elements and near neighbor communications. The architecture evolved is simulated using the Verilog Hardware Description Language. This project should provide a framework for a massively parallel processing architecture for such systems. It is expected that this project will lead to the design and implementation of a real time system.