Electronic systems

Dynamic modeling of Printed Circuit Boards (PCBs) with mounted components, was
investigated via the example of a PC network card by removing components in different stages and
examining the resulting effects on the modal properties. Modal test results were compared with those
from an ANSYS finite element analysis.
Questions considered were: a) Do added components have a significant effect on the modal
properties of a PCB and what are the effects ? b) How much variation is there in natural frequencies
from board to board and test to test for a single board? c) Can a board with attached components
reasonably be modeled as a uniform elastic plate with an "equivalent" density and modulus of
elasticity?
Results obtained indicate that added components do have significant effects on the board
modal properties, less so for the lower modes than for the higher modes. There was only slight
variation in the natural frequencies from board to board and from test to test for a single board. For
the first two modes of vibration, it was found that the board considered could be modeled as a
uniform elastic plate with "equivalent" properties, provided an appropriate value of equivalent elastic
modulus was used. General findings, applicable to any PCB design, are presented.

Implementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis algorithm and a new test generation approach, that are based on topologies rather than individual logic functions. We have found that 19 and 363 DCVS topologies can represent 256 and 65,536 functions, respectively, for the 3- and 4-varaible cases. Physical defect analysis was conducted with the aid of a building block approach to analyze the n-type logic tree and provides a basis for evolving hierarchical test pattern generation for the topologies.