Elkhatib, Rami

Cryptography relies on hard mathematical problems that current conventional computers cannot solve in a feasible amount of time. On the other hand, quantum computers, with their quantum mechanic construction, are presumed to be able to solve some of these problems in a reasonable amount of time. More specifically, the current hard problems that public key cryptography relies upon are expected to be easily broken during the quantum era, a time when large-scale quantum computers are available. To address this problem ahead of time, researchers and institutions have proposed post-quantum cryptography (PQC), which is an area of research that focuses on quantum-resistant public key cryptography algorithms. One of the candidates in the NIST PQC standardization process is SIKE, an isogeny-based candidate. The main advantage of SIKE is that it provides the smallest key size out of all the NIST PQC candidates at the cost of performance. Therefore, the development of hardware accelerators for SIKE is very important to achieve high performance in time-constrained applications. In this thesis, we implement several accelerators for SIKE and its primitives using different design approaches, all of which are suitable for different applications. We deliver significant enhancements to SIKE’s most expensive component, the modular multiplier. We design SIKE using a hardware-based approach and a software-hardware codesign approach, the latter of which utilizes a RISC-V processor. We also design SIKE with multi-level security level support for applications that require support of multiple security levels with minimal area usage. We enclose our performance and area results, which provide a reference to evaluate our work with other implementations.