Rivas-Torres, Wilfredo

Analog CMOS amplifiers are the building blocks for many analog circuit
applications such as Operational Amplifiers, Comparators, Analog to Digital converters
and others. This dissertation presents empirical design methodologies that are both
intuitive and easy to follow on how to design these basic building blocks. The design
method involves two main phases. In the first phase NMOS and PMOS transistor design
kits, provided by a semiconductor foundry, are fully characterized using a set of
simulation experiments. In the second phase the user is capable of modifying all the
relevant circuit design parameters while directly observing the tradeoffs in the circuit
performance specifications. The final design is a circuit that very closely meets a set of
desired design specifications for the design parameters selected. That second phase of the
proposed design methodology utilizes a graphical user interface in which the designer
moves a series of sliders allowing assessment of various design tradeoffs. The theoretical basis for this design methodology involves the transconductance efficiency and inversion
coefficient parameters. In this dissertation there are no restrictive assumptions about the
MOS transistor models. The design methodology can be used with any submicron model
supported by the foundry process and in this sense the methods included within are
general and non-dependent on any specific MOSFET model (e.g. EKV or BSIM3). As
part of the design tradeoffs assessment process variations are included during the design
process rather than as part of some post-nominal-design analysis. One of the central design parameters of each transistor in the circuit is the MOSFET inversion coefficient. The calculation of the inversion coefficient necessitates the determination of an important process parameter known as the Technology Current. In this dissertation a new method to determine the technology current is developed. Y Parameters are used to characterize the CMOS process and this also helps in improving the technology current determination method. A study of the properties of the technology current proves that indeed a single long channel saturated MOS transistor can be used to determine a fixed technology current value that is used in subsequent submicron CMOS
design. Process corners and the variability of the technology current are also studied and
the universality of the transconductance efficiency versus inversion coefficient response
is shown to be true even in the presence of process variability.

Current Mirrors are widely used circuits in IC designs. They are used as current sources and loads. The proper selection of a Current Mirror configuration is therefore important. This thesis reviews critical parameters for Current Minors characterization. Six MOS Current Mirror configurations are studied, and their performance characteristics are compared. The proper selection and use of MOSFET models are presented. It is shown that CAD-based design and analysis is indispensable if realistic MOS models such as BSIM3 are used. The CAD based analysis and design employs simulation parameter tuning, optimization and swept parameters. The presented CAD techniques allow a designer to make important tradeoffs for different configurations. One of the main thesis observations is that it is not always necessary to use more involved Current Mirror configurations; a Simple Current Mirror Configuration is often sufficient. The thesis also studies the adverse effects on the design caused by process variations.