Shankar, Ravi

We explored the possible effects of various interferences on Bluetooth devices in the ISM band. We developed a model of Bluetooth and interference from sources such as WLAN devices and Microwave oven, and evaluate the functionality of Bluetooth in the presence of these interferences. As a first step we created Bluetooth, WLAN and Microwave oven models using SPW (Signal Processing Workstation). In our exploration, we undertake three cases: (1) When the Bluetooth is in the presence of only noises in the channel; (2) When the Bluetooth is in the presence of Microwave oven interference; (3) When the Bluetooth is in the presence of WLAN interference. We show that these models can be used to analyze the interferences on the Bluetooth in the ISM band. Future efforts of our group will be to analyze this Bluetooth model with combined interference from all the sources, to come up with possible solutions to reduce the effect of these interferences.

We explored the portability of various OS concepts to silicon. We wish to develop intellectual property blocks of various OS concepts, so that an embedded system designer has the option to mix and match. As a first step we have looked at inter-process communication (IPC) and Process Scheduling. We have implemented simple hardware building blocks for these. In our problem we utilize two processors, one each assigned as Master and Slave. Master is in control and implements the OS algorithms, while the Slave executes the user/application code. We show that these OS building blocks can be implemented in the hardware. Future effort of our group is to build a portfolio of OS IP blocks and explore optimization for various applications.

The placement problem is an important part in the design process of VLSI chips. It is necessary to have a proper placement so that all connections between modules in a chip can be routed in a minimum area without violating any physical or electrical constraints. Current algorithms either do not give optimum solutions, are computationally slow, or are difficult to parallelize. PIREN(copyright) is a parallel implementation of a force directed algorithm which seeks to overcome the large amount of computer time associated with solving the placement problem. Each active processor in the massively parallel SIMD machine, the MasPar MP-2.2, can perform in parallel the computation necessary to place cells in an optimum location relative to one another based upon the connectivity between cells. This is due to a salient feature of the serial algorithm which allows multiple permutations to be made simultaneously on all modules in order to minimize the objective function. The serial implementation of PIREN(copyright) compares favorably in both run time and layout quality to the simulated annealing based algorithm, TimberWolf3.2$\sp\copyright$. The parallel implementation on the MP-2.2 has a speedup of 4.5 to 58.0 over the serial version of PIREN$\sp\copyright$ running of the VAX 6320, while producing layouts for several MCNC benchmarks which are of the same quality as those produced by the serial implementation.

This study evaluates the use of an electrical impedance
plethysmograph as a noninvasive technique for early detection of
atherosclerosis. The instrument is inexpensive, easily portable and
causes no health risks. Thus, the system is ideally suited for mass
screemng and epidemiological studies, if proven to be effective.
We have conducted experiments usmg a three-channel
impedance plethysmograph once every 8 - 10 weeks on a colony of
20 male cynomolgus monkeys (macaca fascicularis). Five monkeys
were on a control diet (monkey chow) and fifteen on a high
cholesterol diet (1 mg cholesterol/Kcal with 40% of the calories derived from fat). The diet period for the monkeys ranged from 16-28 months (25 months typically).
We wrapped a pressure cuff with one pair of electrodes around
the upper left leg of the monkey. Two other sets of electrodes were
wrapped, one distal to the pressure cuff on the lower left leg and the
other as reference on the upper arm. We measured impedance
pulses at these three different sites simultaneously using a three
channel impedance plethysmograph. The signals were recorded
when the pressure in the pressure cuff was changed from 200 mm
Hg to 20 mm Hg in steps of 10 mm Hg. Arterial volume change was
evaluated from this. Experiments were repeated with the cuffed
segment on the right leg, and then on the left arm.
The arterial volume change vs cuff pressure (V- Pc)
characteristics were used to follow the progression of the disease.
The V- Pc characteristic, initially with a well defined peak, changed
to a flatter characteristic with increased period on the cholesterol
diet. Monkeys on the control diet showed no flattening of the curve
with time. In order to understand theoretically the effect of disease on
the compliance - transmural pressure (C-Pt) characteristic (and hence
V - Pc characteristic), we developed an arterial model to study the
pressure - radius relationship of an artery under different disease
states. We have also developed an expression for the equivalent
incremental modulus of elasticity based on the incremental modulus
of elasticity of the individual arterial wall layers. The resulting expressions were used to study the effect of increase in stenosis and
calcification on the V - Pc and C-Pt characteristics.
The simulation results obtained using the arterial model match
our experimentally observed data of decrease m peak compliance
with disease. The peak compliance was seen to decrease m
amplitude and shift left (towards decreasing transmural pressure) as
the artery got thicker with atherosclerotic disease. The V - Pc
characteristic, initially with a well defined peak, got flatter with
disease.
Our simulation results lead us to believe that the noninvasive
technique 1s sensitive enough to follow progressiOn of the
atherosclerotic disease. Morphometric and histochemical data were
collected subsequent to the sacrifice of the monkeys. Evaluation of these data and correlations with our compliance data will lead us to a more definitive statement on the method's sensitivity.
This however, is beyond the scope of this dissertation.

A VLSI implementable feature extraction scheme, and two VLSI implementable algorithms for feature classification that should lead to a practical handwritten digit recognition system are proposed. The feature extraction algorithm exploits the concept of holon dynamics. Holons can be regarded as a group of cooperative processors with self-organizing property. Two types of artificial neural network-based classifiers have been evolved to classify these features. The United States Post Office handwritten digit database was used to train and test these networks. The first type of classifier system used limited interconnect multi-layer perceptron (LIMP) modules in a hierarchical configuration. Each classifier in this system was independently trained and designated to recognize a particular digit. A maximum of sixty-one digits were used to train and 464 digits which included the training set were used to test the classifiers. A cumulative performance of 93.75% (correctly recognized digits) was recorded. The second classifier system consists of a cluster of small multi-layer perceptron (CLUMP) networks. Each cell in this system was independently trained to trace the boundary between two or more digits in the recognition plane. A combination of these cells distinguish a digit from the rest. This system was trained with 1796 digits and tested on 1918 different set of digits. On the training set a performance of 95.55% was recorded while 79.35% resulted from the test data. These results, which are expected to further improve, are superior to those obtained by other researchers on the same database. This technique of digit recognition is general enough for application in the development of a universal alphanumeric recognition system. A hybrid VLSI system consisting of both analog and digital circuitry, and utilizing both Bi-CMOS and switched capacitor technologies has been designed. The design is intended for implementation with the current MOSIS 2 $\mu$m, double poly, double metal, and p-well CMOS technology. The integrated circuit is such that both classifier systems can be realized using the same chip.

Recently, Artificial Neural Network (ANN) computing systems have become one of the most active and challenging areas of information processing. The successes of experimental neural computing systems in the fields of pattern recognition, process control, robotics, signal processing, expert system, and functional analysis are most promising. However due to a number of serious problems, only small size fully connected neural networks have been implemented to run in real-time. The primary problem is that the execution time of neural networks increases exponentially as the neural network's size increases. This is because of the exponential increase in the number of multiplications and interconnections which makes it extremely difficult to implement medium or large scale ANNs in hardware. The Modular Grouped Weight Quantization (MGWQ) presented in this dissertation is an ANN design which assures that the number of multiplications and interconnections increase linearly as the neural network's size increases. The secondary problems are related to scale-up capability, modularity, memory requirements, flexibility, performance, fault tolerance, technological feasibility, and cost. The MGWQ architecture also resolves these problems. In this dissertation, neural network characteristics and existing implementations using different technologies are described. Their shortcomings and problems are addressed, and solutions to these problems using the MGWQ approach are illustrated. The theoretical and experimental justifications for MGWQ are presented. Performance calculations for the MGWQ architecture are given. The mappings of the most popular neural network models to the proposed architecture are demonstrated. System level architecture considerations are discussed. The proposed ANN computing system is a flexible and a realistic way to implement large fully connected networks. It offers very high performance using currently available technology. The performance of ANNs is measured in terms of interconnections per second (IC/S); the performance of the proposed system changes between 10^11 to 10^14 IC/S. In comparison, SAIC's DELTA II ANN system achieves 10^7. A Cray X-MP achieves 5*10^7 IC/S.

The rapid evolution of silicon technology has brought exponential benefits in cost, scale of integration, power per function, size per function and speed. The ability to place multiple function "systems" on a single silicon chip, reduce development cycle while increasing product functionality, performance and quality. With this increased complexity, ability to model at high level of abstraction becomes crucial. Also, the fact that no known existing complete system on chip design packages with perfect tools, models, and formalisms further slows down and complicates the development. This dissertation provides an integrated environment for hardware software co-design at a high level of abstraction. We have developed a SystemC based cockpit for this purpose. The cockpit, known as SHINE consists of many components including architectural components, operating system components, and application software components. The ability to represent and manipulate these components at high levels of abstraction is a major challenge. To address these challenges we have developed a set of principles. Important principles evolved are synergy of separation of concerns, reusability, flexibility, ease of use, and support for multiple levels of abstraction. 'Synergy of Separation of Concerns' helps in maintaining transparency during all instances in the development of the integrated environment. One application is transparent to another application and in turn to the system architecture. Also in the system architecture, each module is designed independent of other modules. Well defined interfaces enable this transparency and easier to integrate. This also enhances component reuse and overall design environment modularity. 'Ease of Use' allows the user to shorten the learning curve involved. In SHINE, 'Flexibility' is addressed via support for plug-and-play of components in the design environment. We provide results to show the implementation of these principles. SHINE provides a cost-effective mechanism to develop a system co-design infrastructure. This will lead to early system verification and performance estimation resulting in shorter time-to-market. The design flow developed is structured and is easily extended. This is an exploratory study that is the result of a long term industrial collaboration to enhance design productivity. Significantly more work lies ahead in developing an industry standard tool and methodology.

Many wireless network applications, such as wireless computing on local area networks, employ data throughput as a primary performance metric. The data throughput on such networks has therefore been increasing in recent years. However, there are other potential wireless network applications, such as industrial monitoring and control, consumer home automation, and military remote sensing, that have relaxed throughput requirements, often measured in bits/day. Such networks have power consumption and cost as primary performance metrics, rather than data throughput, and have been called wireless sensor networks. This work describes a physical layer, a data link layer, and a network layer design suitable for use in wireless sensor networks. To minimize node duty cycle and therefore average power consumption, while minimizing the symbol rate, the proposed physical layer employs a form of orthogonal multilevel signaling in a direct sequence spread spectrum format. Results of Signal Processing Worksystem (SPW, Cadence, Inc.) simulations are presented showing a 4-dB sensitivity advantage of the proposed modulation method compared to binary signaling, in agreement with theory. Since the proposed band of operation is the 2.4 GHz unlicensed band, interference from other services is possible; to address this, SPW simulations of the proposed modulation method in the presence of Bluetooth interference are presented. The processing gain inherent in the proposed spread spectrum scheme is shown to require the interferer to be significantly stronger than the desired signal before materially affecting the received bit error rate. The proposed data link layer employs a novel distributed mediation device (MD) technique to enable networked nodes to synchronize to each other, even when the node duty cycle is arbitrarily low (e.g., <0.1%). This technique enables low-cost devices, which may employ only low-stability time bases, to remain asynchronous to one another, becoming synchronized only when communication is necessary between them. Finally, a wireless sensor network design is presented. A cluster-type architecture is chosen; the clusters are organized in a hierarchical tree to simplify the routing algorithm. Results of several network performance metrics simulations, including the effects of the distributed MD dynamic synchronization scheme, are presented, including the average message latency, node duty cycle, and data throughput. The architecture is shown to represent a practical alternative for the design of wireless sensor networks.