Shankar, Ravi

We have developed a high signal to noise ratio automatically resetting electrical impedance plethysmograph for noninvasive determination of blood pressure in pigeons. Pigeons are finding increased use as an economical and appropriate animal model for the study of human atherosclerosis. The impedance plethysmograph obtains the pulsatile arterial volume change as an impedance pulse. Nyboer's equation may then be used to extract the arterial volume change from the impedance pulse. The designed impedance plethysmograph has a sensitivity of 430 mV/m$\Omega$ and a noise level of 0.12 m$\Omega$ peak-to-peak, significantly better than systems reported earlier. Refinements to further enhance the performance are also presented.

This microprocessor based drug infusion control system is intended to aid doctors and nurses in the care of critically ill cardiac patients. The patient's arterial blood pressure is monitored and the infusion rate of the vasodilator sodium nitroprusside is regulated based on a model reference adaptive control algorithm. The algorithm employs a reference model to approximate the patient drug response. The reference model output is compared with the patient blood pressure change and the adaptive controller parameters are changed bringing the patient drug response in closer agreement with the reference model. Drug infusion is digitally controlled by a microprocessor based system and employs a stepper motor driven peristaltic pump. Simulation studies have validated the system. Animal experiments and clinical studies will be conducted later.

A PCM MF Receiver based on either analog or digital filters
results in a fairly large chip. A recent publication attempts to
address this issue by using certain approximations that replace
multiplications with simple additions and subtractions. This results
in a significantly smaller chip. In our research, we have further
refined/changed the algorithms and approximations in order to reduce
the chip size further and the chip count to one.
A simulation model corresponding to this, written in ISPS and
Fortran, was extensively utilized to verify that the proposed
receiver would meet and/or exceed all the commercial specifications.
Subsequent to that, we initiated hardware design using structured
methodologies. Hardware modules written in a high-level hardware
description language have been simulated for functional validity. We
expect to utilize mixed mode simulations and hierarchical design
concepts in translating this high-level description to a hardware
implementation on a semi-custom CMOS chip.

In this study, electrical impedance plethysmograph was used to measure
the nonlinear elastic properties of the leg arteries. Two methods
were used. In method one, a pressure cuff was wrapped around the
lower leg and the recordings were made from under the cuff. Also a
second set of recordings were made at a site distal to the cuff, to
determine the attenuation of blood pressure pulse by the cuff at cuff
pressures above diastolic. In method 2 an Inverter was used and
recordings were made from the same segment. Also recordings were made
from the upper arm at the heart level to define the blood pressure
pulse, that causes the volume change in the leg arteries. A wide
range of pressures were used and V-P and compliance curves were
calculated with both the methods. In order to improve the accuracy
and reduce operator errors, a personal computer based data acquisition
and processing system was developed.

The concept of a Reduced Instruction Set Computer
(RISC) has evolved out of a desire to enhance the performance
of a computer. We present here a detailed design of a
Testable Reduced Instruction Set Computer (TRISC) that utilizes
a Multiple Register Set. Level Sensitive Scan Design
(LSSD) is used to incorporate testability into our design.
We first evolved a functional description of the design
using Digital Design Language (DDL) a hardware programming
language. We then entered the schematic of the design into
Daisy's Logician V, a CAD/CAE workstation, using NCR CMOSII
Digital Standard Cell Library. We then performed a unit
delay simulation on the hierarchical design database to
ascertain the logical functioning of the system.

Current multicore processors attempt to optimize consumer experience via task partitioning and concurrent execution of these (sub)tasks on the cores. Conversion of sequential code to parallel and concurrent code is neither easy, nor feasible with current methodologies. We have developed a mapping process that synergistically uses top-down and bottom-up methodologies. This process is amenable to automation. We use bottom-up analysis to determine decomposability and estimate computation and communication metrics. The outcome is a set of proposals for software decomposition. We then build abstract concurrent models that map these decomposed (abstract) software modules onto candidate multicore architectures; this resolves concurrency issues. We then perform a system level simulation to estimate concurrency gain and/or cost, and QOS (Qualify-of-Service) metrics. Different architectural combinations yield different QOS metrics; the requisite system architecture may then be chosen. We applied this 'middle-out' methodology to optimally map a digital camera application onto a processor with four cores.

High speed low power scalable multiplier is needed in computation intensive DSP applications such as video and image compression algorithms. We used an algorithm that folds the larger bit-width operands so smaller bit-width multipliers can be used. Successive folding on operands can be done until a desired threshold is reached. This method has inherent advantages of reuse of optimized building blocks, dynamic reconfiguration, and low power. We implemented a hardware multiplier based on this algorithm using Verilog hardware description language. Our results show that this multiplier exhibited significant power advantage over Array and Wallace Tree multipliers for comparable speeds, but had higher gate counts.

Signal Integrity is a major bottleneck for DSM designs. Signal integrity refers to wide variety of problems, which leads to misconception. Signal integrity causes delay or noise at the high-level, but this boils down to resistance, capacitance and inductance (RLC) at circuit level. Several analysis and reduction techniques were proposed for reducing these effects on signal integrity. This work solves the misconception by encompassing different problems Chat effect signal integrity and can be good reference for a integrated circuit designer. The objective is to analyze these modeling methods, reduction techniques, tools and make recommendations that aids in developing a methodology for perfect design closure with an emphasis on signal integrity. These recommendations would form a basis for developing a methodology to analyze interference effects at higher levels of abstraction.

Technological advances are providing us with the capability to integrate more and more functionality into a single chip. This is leading to a new design paradigm, System On a Chip (SoC). SoC design brings with it new challenges and difficulties. Managing these challenges and complexity necessitate modeling of systems at a hierarchy of abstraction levels starting from System Level down to Register Transfer Level. Using a single language across all these levels would ensure that the models are consistent and error-free. SystemC is one such language that has the infrastructure for specifying the design at System level, Behavioral level and RT levels of abstraction. This thesis showcases the same using two design examples---Simplex Data Protocol and General Purpose Timer (GPT) peripheral. Coding style and level of detailing at different levels are shows. Process of refining from one level to another is illustrated. GPT peripheral module designed in this thesis work can be further reused as a timer library component in system architectures.