Operating systems (Computers)

Enhanced system design productivity is key to satisfying time-to-market demands. One
will have to exploit design reuse methodology to meet project schedule requirements.
Integration of components often fails due to various concurrency violations.
Concurrency issues arise when components executing in parallel share resources and
interact with each other. Such a system may have intermittent, yet catastrophic failures,
if these concurrency issues are not addressed properly. In this thesis, we propose a
methodology for developing concurrency compliant components from a requirement
document. We have applied this methodology for developing process management and
memory management aspects of a Real Time Operating System (RTOS). In this
methodology, we start from a "customer' s" requirement document that is then mapped to
activity diagram, swimlane diagram, class diagrams, and use case diagrams. To evolve a
concurrency compliant design, we use the Message Sequence Chart plug-in for the
Labeled Transition State Analyzer (LTSA). This plug-in lets us use Message Sequence
Charts rather than coding in Finite State Processes (FSP). Later, we use MLDesigner to
simulate our R TOS sub-system and demonstrate proper behavior of this sub-system.

We present an implementation of the IEEE WAVE (Wireless Access in Vehicular Environments) 1609.4 standard, Multichannel Operation. This implementation provides concurrent access to a control channel and one or more service channels, enabling vehicles to communicate among each other on multiple service channels while
still being able to receive urgent and control information on the control channel. Also
included is functionality that provides over-the-air timing synchronization, allowing
participation in alternating channel access in the absence of a reliable time source.
Our implementation runs on embedded Linux and is built on top of IEEE 802.11p, as
well as a customized device driver. This implementation will serve as a key compo-
nent in our IEEE 1609-compliant Vehicular Multi-technology Communication Device
(VMCD) that is being developed for a VANET testbed under the Smart Drive initiative, supported by the National Science Foundation.

In this thesis, we measure and analyze the effects of compression in a demand paging operating system. We first explore existing compression algorithms and page replacement policies currently in use. Then we examine the OS/2 operating system which is modified to include page-based compression. Software trace hooks are inserted into the operating system to determine the amount of time required to process a page fault for each type of page, e.g. non-compressed, compressed, zero-filled, and the number of page faults for each type of page. Software trace measurements as well as physical timings are taken on a system without compressed pages and the same system with compressed pages. We find the system with compressed pages shows a slight increase in paging activity for memory constrained systems, but performance (time) is improved in both memory constrained and unconstrained systems.

Compared to the traditional wireless network, the multi-hop ad hoc wireless network (simply called ad hoc networks) is self-configurable, dynamic, and distributed. During the past few years, many routing protocols have been proposed for this particular network environment. While in wired and optical networks, multi-protocol label switching (MPLS) has clearly shown its advantages in routing and switching such as flexibility, high efficiency, scalability, and low cost, however MPLS is complex and does not consider the mobility issue for wireless networks, especially for ad hoc networks. This thesis migrates the label concept into the ad hoc network and provides a framework for the efficient Label Routing Protocol (LRP) in such a network. The MAC layer is also optimized with LRP for shorter delay, power saving, and higher efficiency. The simulation results show that the delay is improved significantly with this cross-layer routing protocol.

We explored the portability of various OS concepts to silicon. We wish to develop intellectual property blocks of various OS concepts, so that an embedded system designer has the option to mix and match. As a first step we have looked at inter-process communication (IPC) and Process Scheduling. We have implemented simple hardware building blocks for these. In our problem we utilize two processors, one each assigned as Master and Slave. Master is in control and implements the OS algorithms, while the Slave executes the user/application code. We show that these OS building blocks can be implemented in the hardware. Future effort of our group is to build a portfolio of OS IP blocks and explore optimization for various applications.

The Transmission Control Protocol (TCP) is one of the core protocols of the Internet protocol suite. In the wired network, TCP performs remarkably well due to its scalability and distributed end-to-end congestion control algorithms. However, many studies have shown that the unmodified standard TCP performs poorly in networks with large bandwidth-delay products and/or lossy wireless links. In this thesis, we analyze the problems TCP exhibits in the wireless communication and develop TCP congestion control algorithm for mobile applications. We show that the optimal TCP congestion control and link scheduling scheme amounts to window-control oriented implicit primaldual solvers for underlying network utility maximization. Based on this idea, we used a scalable congestion control algorithm called QUeueIng-Control (QUIC) TCP where it utilizes queueing-delay based MaxWeight-type scheduler for wireless links developed in [34]. Simulation and test results are provided to evaluate the proposed schemes in practical networks.