Mahgoub, Imad

Today's Personal Computers (PC) do more work and hence hold more important and meaningful data than before. This demands the necessity of better PC data protection services. In this concern we surveyed three major PC data protection tools, namely, Seagate Corporation's Client-Exec, Computer Associates Cheyenne Backup, Xpoint Technologies Uptime and analyzed them in terms of Restore Time and Total Cost of Ownership. Though these standalone tools are good in terms of PC data protection, IT managers still prefer Enterprise tools because they offer better services in terms of usability, manageability and platform independency. Combining the two tools will benefit each other. Hence we developed a solution to this problem by integrating these two types of tools. Integration of third party products with System Management Server (SMS) extended its services. But in order to make this integration generic, independent of the Enterprise tool, Web Based Enterprise Management integration strategy is adopted. Integration with Adstar Distributed Storage Manager (ADSM) extended services of the third party product. Integration of third party products with SMS and ADSM combined the benefits of the two and WBEM integration showed that this is the future direction.

In this present computer age, cellular technology and portable computers are becoming an integral part of day to day life. Each computer user wants to access the computing resources, irrespective of the location. Because of this need the computing paradigm "Mobile Computing" has assumed a primary role in modern computer communication technology. There are different Internet protocols proposed for Mobile Computing. In the present research, we study the Internet Engineering Task Force (IETF) Mobile IPv6 (new version of current IPv4 protocol). We have developed simulation program using Scientific and Engineering Software (SES/workbench) and studied three mobility patterns namely Travelling Salesman, Pop-Up and Boring Professor for the performance study of Mobile IPv6. Performance of Mobile IPv6 is measured in terms of utilization and overhead and compared with Mobile IPv4 and Basic Triangular Routing (BTR). It has been observed that Mobile IPv6 scheme has better route optimization than the other schemes when Mobile node's movement from one network to another network is less frequent. But, when the movement of the Mobile node is more frequent then Basic Triangular Routing scheme outperformed the Mobile IPv6 scheme.

This research investigates memory latency of cluster-based cache-coherent multiprocessor systems with different interconnection topologies. We focus on a cluster-based architecture which is a variation of Stanford DASH architecture. The architecture, also, has some similarities with the STiNG architecture from Sequent Computer System Inc. In this architecture, a small number of processors and a portion of shared-memory are connected through a bus inside each cluster. As the number of processors per cluster is small, snoopy protocol is used inside each cluster. Each processor has two levels of caches and for each cluster a separate directory is maintained. Clusters are connected using directory-based scheme through an interconnection network to make the system scaleable. Trace-driven simulation has been developed to evaluate the overall memory latency of this architecture using three different network topologies, namely ring, mesh, and hypercube. For each network topology, the overall memory latency has been evaluated running a representative set of SPLASH-2 applications. Simulation results show that, the cluster-based multiprocessor system with hypercube topology outperforms those with mesh and ring topologies.

The use of cache memories in multiprocessor systems increases the overall systems performance. Caches reduce the amount of network traffic and provide a solution to the memory contention problem. However, caches introduce memory consistency problems. The existence of multiple cache copies of a memory block will result in an inconsistent view of memory if one processor changes a value in its associated cache. Cache coherence protocols are algorithms designed in software or hardware to maintain memory consistency. With the increased complexity of some of the more recent protocols, testing for the correctness of these protocols becomes an issue that requires more elaborate work. In this thesis, correctness analysis of a selected group of representative cache coherence protocols was performed using Petri nets as a modeling and analysis tool. First, the Petri net graphs for these protocols were designed. These graphs were built by following the logical and coherence actions performed by the protocols in response to the different processors' requests that threatens memory consistency. Correctness analysis was then performed on these graphs.

Many image processing applications can exploit high degree of data locality and parallelism to improve performance. Customized massively parallel computing hardware provides expensive but the most efficient solution as far as performance is concerned. Now-a-days high bandwidth network with high performance workstations are becoming economical and are widely available. Hence, better performance-to-cost ratio can be achieved by implementing message passing paradigm of parallel processing. Parallel edge detector was developed using message passing interfaces on cluster of workstations. This thesis discussed performance evaluation in terms of execution time, speedup, and efficiency for tasks with different computational intensities. Effects of sequential I/O component and load balancing are also discussed.

In this thesis, a delta service extends a mobile file system cache in order to minimize the amount of data transferred over wireless communications links. Network bandwidth stands as one of the resource limitations impacting the design of mobile computer applications. At the mobile file system service level, caching and compression provide resource conservation in distributed applications. This thesis proposes a delta service to enhance caching services characteristic of mobile computer file systems. Well established a mechanisms for sequence comparison and software configuration management, file deltas have applicability to mobile computer and distributed file system caching environments. Study of the delta service uses trace-driven simulation methodology incorporating traces obtained in a real world distributed environment. A mobile computer client cache model will corroborate existing studies regarding suitable cache size for disconnected client operation. A delta service model will extend the mobile computer client cache model of various cache sizes in order to gauge the bandwidth savings on the link obtained by the delta service.

In this study, a tool has been developed which traces the storage subsystem workload at the subsystem level. Due to hardware assistance, this tool has very little overhead. This is achieved by incorporating the tracing routine in the microcode of the IBM SCSI adapter. The I/O traces are collected, in realtime, on a PS/2 connected to the modified SCSI adapter via an asynchronous link. These traces are then processed and studied. We have developed a scheme to characterize the workload by studying the parameters of the traced workload. These parameters include LBA distributions, interarrival time distribution, size distributions, ratios between read requests and write requests, adapter's cache performance, etc. In this study, workload characterization of storage subsystems in OS/2, AIX and NetWare environments was performed. An algorithm for synthesizing of the workload was also developed and implemented as part of this study.

A user interface that has objects familiar to the user will be easier to use. In this thesis, a user interface that is customizable to any color bitmap is proposed. The most significant problem with this approach is the problem of finding objects in a color bitmap. A solution to the problem is proposed and evaluated using an analysis tool, developed for this thesis, called Workbench. Current image detection methods are evaluated and compared to the solution proposed using Workbench. The proposed solution is then evaluated for the YIQ and HSI color mappings. The results of this investigation and recommendations for future work is proposed.

Caches are used in shared memory multiprocessors to reduce the effective memory latency, and network and memory bandwidth requirements. But the data spreading across the caches leads to the cache coherence problem. In this thesis, a new directory based cache coherence scheme, called the cache-vector protocol, is proposed and evaluated. The said scheme entails a low memory overhead but delivers a performance that is very close to that of the scheme proposed by Censier and Feautrier (3), which offers the best performance of all the directory based schemes. The performance of the cache-vector protocol is evaluated using trace-driven simulation. A figure of merit which takes into account the average memory latency, network traffic and the hardware overhead is introduced and used as the basis of comparison between the two schemes. The simulation results indicate that the cache-vector protocol is a viable solution to the cache coherence problem in large scale multiprocessors.

This thesis introduced two allocation schemes for cache memory in multiprogramming environments. The proposed schemes, called static and dynamic cache partitioning, are slight variations of the schemes proposed by Thiebaut and Stone. We developed a trace driven simulation program to study and compare the performance of the proposed schemes to that of the cache sharing and cache flushing schemes. Furthermore, we proposed a new replacement technique that uses some heuristic to detect loop structures in the reference patterns. Initially, the proposed technique uses the Least Recently Used (LRU) strategy. Once a loop has been detected, all the instructions, which will harm performance if they were to be stored in the cache, will be dynamically excluded from being cached. The LRU strategy will resume as soon as the end of the loop has been detected. We have also developed a simulation program to compare the performance of this scheme to that of other related ones, so as to demonstrate its effectiveness. The results show our scheme outperforms the others, especially when the system references are loop dominated.