Computer-aided design

As a compamon and complement to the work being done to build a secure systems
methodology, this thesis evaluates the use of Model-Driven Architecture (MDA) in
support of the methodology's lifecycle. The development lifecycle illustrated follows the
recommendations of this secure systems methodology, while using MDA models to
represent requirements, analysis, design, and implementation information. In order to
evaluate MDA, we analyze a well-understood distributed systems security problem,
remote access, as illustrated by the internet "secure shell" protocol, ssh. By observing the
ability of MDA models and transformations to specify remote access in each lifecycle
phase, MDA's strengths and weaknesses can be evaluated in this context. A further aim
of this work is to extract concepts that can be contained in an MDA security metamodel
for use in future projects.

In the globalization software development environments, where the development
activities are distributed geographically and temporally, it is increasingly important
for the Computer Aided Software Engineering (CASE) tools to maintain the
information (both syntactic and semantic) captured in the design models. The Unified
Modeling Language (UML) is the de facto standard for modeling software
applications and UML diagrams serve as graphical documentations of the software
system. The interoperability of UML modeling tools is important in supporting the
models exchange, and further support design reuse. Tool interoperability is often
implemented using XML Metadata Interchange (XMI). Unfortunately, there is a loss
of fidelity of the design documentation when transforming between UML and XMI
due to the compatibility of different versions of UML, XMI and add-on proprietary
information, which hinder reuse. This thesis evaluates the interoperability of UML
modeling tools by assessing the quality of XMI documents representing the design.
Case studies in this thesis demonstrate a framework of preserving the fidelity of UML
model 's data when importing and exporting different UML models in a distributed
heterogeneous environment.

This thesis presents a methodology of Comparative Analysis of different Design for Assembly (DFA) Methods. Three DFA methods, Boothroyd's Design for Assembly, Design for Assembly Guidelines and Value Analysis are compared. A "Select DFA Software," is developed using Turbo C++, which would enable a product designer to make a comparative analysis of different DFA methods from which the designer can chose from. In using the Software the designer is not required to know in detail the different DFA methods. Responses to, easy to understand factors that affect the selection of a DFA method enables the designer to use the Software meaningfully. Two case studies are conducted for application of the DFA Software and the three different DFA methods.

Software reuse has been looked upon in recent years as a promising mechanism for achieving increased levels of software quality and productivity within an organization. A form of software reuse which has been gaining in popularity is the use of design patterns. Design patterns are a higher level of abstraction than source code and are proving to be a valuable resource for both software developers and new hires within a company. This thesis develops the idea of applying design patterns to the Computer Aided Design (CAD) software development environment. The benefits and costs associated with implementing a software reuse strategy are explained and the reasoning for developing design patterns is given. Design patterns are then described in detail and a potential method for applying design patterns within the CAD environment is demonstrated through the development of a CAD design pattern catalog.

The techniques employed in integrated circuit (IC) design have advanced significantly in the past decade. Design automation tools now offer hardware description languages (HDLs) for modeling and testing new designs. Some tools can even synthesize an IC from a model written in an HDL. Such design tools promise to facilitate greatly the development of new IC designs. They also make it possible for engineering students to learn advanced techniques of IC design and computer architecture in a classroom setting. Two examples of such state-of-the-art design tools are Design Framework and Epoch. In this work, we present a hierarchical design for a reduced-instruction-set computer (RISC) processor, which we implemented using Design Framework and Epoch. The processor is based on the DLX architecture proposed by Hennessy and Patterson. We implemented our design according to a top-down methodology, which worked very well in these design tools.

For certain wavelength size objects, the frequency range between 100 MHz and 1000 MHz spans a transition region when using low frequency electromagnetic scattering codes based on Method of Moments (MoM) to high frequency codes based on Physical Theory of Diffraction (PTD) and ray tracing techniques. As the wavelength size of the object increased, MoM codes can require prohibitively long computational times and hence the more approximate high frequency codes become more attractive. The Ohio State Material Wire code (MATWRS) was selected as a representative MoM code for characterizing the transition region. XPATCH was selected as a representative high frequency code with ACAD used as the general modeling program. To evaluate these codes, a comparison of Radar Cross Section (RCS) predictions for simple PEC canonical shapes was made. Comparisons were made to both measured data where available and predictions generated by the McDonnell Douglas Body of Revolution (BOR) code.

Implementation of CMOS combinational logic with Differential Cascode Voltage Switch logic (DCVS) may have many advantages over the traditional CMOS logic approaches with respect to device count, layout density and timing. DCVS is an ideal target technology for a logic synthesis system in that it provides a complete function cover by providing the function and its complement simultaneously. DCVS is also more testable due to this. We have developed for IBM's DCVS technology a synthesis algorithm and a new test generation approach, that are based on topologies rather than individual logic functions. We have found that 19 and 363 DCVS topologies can represent 256 and 65,536 functions, respectively, for the 3- and 4-varaible cases. Physical defect analysis was conducted with the aid of a building block approach to analyze the n-type logic tree and provides a basis for evolving hierarchical test pattern generation for the topologies.

A PC-based Expert System that uses symbolic manipulations and an inference engine rule-based system to solve direct and inverse kinematics of revolute-jointed manipulators of arbitrary configuration is presented and discussed. Similar applications in the areas of Discrete Signal Processing and Optimal Control are analyzed.

The present trend in manufacturing technology indicates strong tendencies to integrate computer aided design (CAD) and computer aided manufacturing (CAM) to attain the computer integrated manufacturing (CIM) system. Computer aided process planning (CAPP) system serves as the key linkage that interfaces CAD and CAM. In this research, a CAPP system, namely, RD-CAPP was developed using the variant process planning approach. This system is used to generate process plans automatically. The RD-CAPP system developed during this research uses group technology (GT) concepts and a relational data model. The application of the relational database management system and GT provides various advantages such as ease of information management, ease of modification and updating of information stored, ease of interlinking of various databases, etc. The effectiveness of the system described has been verified through the use of industrial data. The results of the study along with the development of various modules and the computer programs are discussed in this thesis.

The costs associated with the design and manufacture of machined components can be significantly reduced by the ability to identify and group similar parts. This activity is generally accomplished by assigning each part a Group Technology code number based on its most significant characteristics. Attempts to accomplish this are hindered by: the relatively small amount of information that can be encoded in a code of manageable length, inconsistencies in human interpretation of design and manufacturing data, the commitment of resources required to review and encode all candidate components at a facility, and the heuristic nature of determining what constitutes significant similarity for any particular application. These problems are addressed by the development of a system that assists in the determination of similarity by comparing CAD (Computer Aided Design) files, rather than Group Technology codes, in a manufacturing oriented frame-based system.