Publisher
Florida Atlantic University
Description
A PCM MF Receiver based on either analog or digital filters
results in a fairly large chip. A recent publication attempts to
address this issue by using certain approximations that replace
multiplications with simple additions and subtractions. This results
in a significantly smaller chip. In our research, we have further
refined/changed the algorithms and approximations in order to reduce
the chip size further and the chip count to one.
A simulation model corresponding to this, written in ISPS and
Fortran, was extensively utilized to verify that the proposed
receiver would meet and/or exceed all the commercial specifications.
Subsequent to that, we initiated hardware design using structured
methodologies. Hardware modules written in a high-level hardware
description language have been simulated for functional validity. We
expect to utilize mixed mode simulations and hierarchical design
concepts in translating this high-level description to a hardware
implementation on a semi-custom CMOS chip.
Note
College of Engineering and Computer Science
Extension
FAU
FAU
admin_unit="FAU01", ingest_id="ing1508", creator="staff:fcllz", creation_date="2007-07-19 02:29:35", modified_by="staff:fcllz", modification_date="2011-01-06 13:08:58"
Person Preferred Name
CHENTHANAKIJ, APICHAI.
Graduate College
Use and Reproduction
Copyright © is held by the author, with permission granted to Florida Atlantic University to digitize, archive and distribute this item for non-profit research and educational purposes. Any reuse of this item in excess of fair use or other copyright exemptions requires permission of the copyright holder.
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Physical Location
Florida Atlantic University Libraries