Integrated circuits

Field output factors (OF) for photon beams from a 6 MV medical accelerator
were measured using five different detectors in a scanning water phantom. The
measurements were taken for square field sizes of integral widths ranging from 1 cm to
10 cm for two reference source-to-surface distances (SSD) and depths in water. For the
diode detectors, square field widths as small as 2.5 mm were also studied. The photon
beams were collimated by using either the jaws or the multileaf collimators. Measured
OFs are found to depend upon the field size, SSD, depth and also upon the type of beam
collimation, size and type of detector used. For field sizes larger than 3 cm x 3 cm, the
OF measurements agree to within 1% or less. The largest variation in OF occurs for jawsshaped field of size 1 cm x 1cm, where a difference of more than 18% is observed.

Recently developed electronic packages called Overmolded Pad Array Chip Carrier (OMPAC) IC packages frequently fail at the interface between the overmold compound and the substrate. In this study, this generic type of structure was evaluated by a combination of experimental and analytical methods. Model specimens representative of OMPAC structures were designed, manufactured and tested to failure. Detailed finite element models of the specimens were developed and analyses conducted to calculate debond stresses. Analytical methods were refined to include the effect of stress singularities. Stress results were averaged over a distance of.010 in. around the stress singularities to capture the intensity of the stress. These results were used in a combined stress failure criterion to calculate interfacial strengths based on macroscopic failure loads. The interfacial strengths were found to approach, but not exceed, those of the bulk overmold compound.

The fundamental goal of a machine vision system in the inspection of an assembled printed circuit board is to locate the integrated circuit(IC) components. These components are then checked for their position and orientation with respect to a given position and orientation of the model and to detect deviations. To this end, a method based on a modified two-level correlation scheme is presented in this thesis. In the first level, Low-Level correlation, a modified two-stage template matching method is proposed. It makes use of the random search techniques, better known as the Monte Carlo method, to speed up the matching process on binarized version of the images. Due to the random search techniques, there is uncertainty involved in the location where the matches are found. In the second level, High-Level correlation, an evidence scheme based on the Dempster-Shafer formalism is presented to resolve the uncertainty. Experiment results performed on a printed circuit board containing mounted integrated components is also presented to demonstrate the validity of the techniques.

Current Mirrors are widely used circuits in IC designs. They are used as current sources and loads. The proper selection of a Current Mirror configuration is therefore important. This thesis reviews critical parameters for Current Minors characterization. Six MOS Current Mirror configurations are studied, and their performance characteristics are compared. The proper selection and use of MOSFET models are presented. It is shown that CAD-based design and analysis is indispensable if realistic MOS models such as BSIM3 are used. The CAD based analysis and design employs simulation parameter tuning, optimization and swept parameters. The presented CAD techniques allow a designer to make important tradeoffs for different configurations. One of the main thesis observations is that it is not always necessary to use more involved Current Mirror configurations; a Simple Current Mirror Configuration is often sufficient. The thesis also studies the adverse effects on the design caused by process variations.

Cache memory is used, in most single-core and multi-core processors, to improve performance by bridging the speed gap between the main memory and CPU. Even though cache increases performance, it poses some serious challenges for embedded systems running real-time applications. Cache introduces execution time unpredictability due to its adaptive and dynamic nature and cache consumes vast amount of power to be operated. Energy requirement and execution time predictability are crucial for the success of real-time embedded systems. Various cache optimization schemes have been proposed to address the performance, power consumption, and predictability issues. However, currently available solutions are not adequate for real-time embedded systems as they do not address the performance, power consumption, and execution time predictability issues at the same time. Moreover, existing solutions are not suitable for dealing with multi-core architecture issues. In this dissertation, we develop a methodology through cache optimization for real-time embedded systems that can be used to analyze and improve execution time predictability and performance/power ratio at the same time. This methodology is effective for both single-core and multi-core systems. First, we develop a cache modeling and optimization technique for single-core systems to improve performance. Then, we develop a cache modeling and optimization technique for multi-core systems to improve performance/power ratio. We develop a cache locking scheme to improve execution time predictability for real-time systems. We introduce Miss Table (MT) based cache locking scheme with victim cache (VC) to improve predictability and performance/power ratio. MT holds information about memory blocks, which may cause more misses if not locked, to improve cache locking performance.

The aim of this work is to investigate an algebraic attack on block ciphers called Multiple Right Hand Sides (MRHS). MRHS models a block cipher as a system of n matrix equations Si := Aix = [Li], where each Li can be expressed as a set of its columns bi1, . . . , bisi . The set of solutions Ti of Si is dened as the union of the solutions of Aix = bij , and the set of solutions of the system S1, . . . , Sn is dened as the intersection of T1, . . . , Tn. Our main contribution is a hardware platform which implements a particular algorithm that solves MRHS systems (and hence block ciphers). The case is made that the platform performs several thousand orders of magnitude faster than software, it costs less than US$1,000,000, and that actual times of block cipher breakage can be calculated once it is known how the corresponding software behaves. Options in MRHS are also explored with a view to increase its efficiency.