GMDH algorithms

The existing Group Method of Data Handling (GMDH) algorithm has characteristics that are ideal for neural network design. This thesis introduces a new algorithm that applies some of the best characteristics of GMDH to neural network design and develops a Pruning based Regenerated Network by discarding the neurons in a layer which don't contribute for the creation of neurons in next layer. Unlike other conventional algorithms, which generate a network which is a black box, the new algorithm provides visualization of the network displaying all the neurons in the network. The algorithm is general enough that it will accept any number of inputs and any sized training set. To show the flexibility of the Pruning based Regenerated Network, this algorithm is used to analyze different combinations of drugs and determine which pathways in these networks interact and determine the combination of drugs that take advantage of these interactions to maximize a desired effect on genes.

In this thesis, application of GMDH Algorithm to real life problems is studied. A particular type of GMDH Algorithm namely TMNN is chosen for this purpose. An effort is made to forecast S&P Index Closing Value with the help of the forecaster. The performance of the TMNN Algorithm is simulated by implementing a tool in C++ for developing forecast models. The validation of this simulation tool is carried out with Sine Wave Values and performance analysis is done in a noisy environment. The noisy environment tests the TMNN forecaster for its robustness. The primary goal of this research is to develop a simulation software based on TMNN Algorithm for forecasting stock market index values. The main inputs are previous day's closing values and the output is predicted closing index.

Researchers from a wide range of fields have discovered the benefits of applying neural networks to pattern recognition problems. Although applications for neural networks have increased, development of tools to design these networks has been slower. There are few comprehensive network development methods. Those that do exist are slow, inefficient, and application specific, require predetermination of the final network structure, and/or result in large, complicated networks. Finding optimal neural networks that balance low network complexity with accuracy is a complicated process that traditional network development procedures are incapable of achieving. Although not originally designed for neural networks, the Group Method of Data Handling (GMDH) has characteristics that are ideal for neural network design. GMDH minimizes the number of required neurons by choosing and keeping only the best neurons and filtering out unneeded inputs. In addition, GMDH develops the neurons and organizes the network simultaneously, saving time and processing power. However, some of the qualities of the network must still be predetermined. This dissertation introduces a new algorithm that applies some of the best characteristics of GMDH to neural network design. The new algorithm is faster, more flexible, and more accurate than traditional network development methods. It is also more dynamic than current GMDH based methods, capable of creating a network that is optimal for an application and training data. Additionally, the new algorithm virtually guarantees that the number of neurons progressively decreases in each succeeding layer. To show its flexibility, speed, and ability to design optimal networks, the algorithm was used to successfully design networks for a wide variety of real applications. The networks developed using the new algorithm were compared to other development methods and network architectures. The new algorithm's networks were more accurate and yet less complicated than the other networks. Additionally, the algorithm designs neurons that are flexible enough to meet the needs of the specific applications, yet similar enough to be implemented using a standardized hardware cell. When combined with the simplified network layout that naturally occurs with the algorithm, this results in networks that can be implemented using Field Programmable Gate Array (FPGA) type devices.

During the Leukocytapheresis (LCAP) process used to treat patients suffering from acute Ulcerative Colitis, medical practitioners have to continuously monitor the Hematocrit (Ht) level in the blood to ensure it is within the acceptable range. The work done, as a part of this thesis, attempts to create an early warning system that can be used to predict if and when the Ht values will deviate from the acceptable range. To do this we have developed an algorithm based on the Group Method of Data Handling (GMDH) and compared it to other Neural Network algorithms, in particular the Multi Layer Perceptron (MLP). The standard GMDH algorithm captures the fluctuation very well but there is a time lag that produces larger errors when compared to MLP. To address this drawback we modified the GMDH algorithm to reduce the prediction error and produce more accurate results.

Design of intelligent systems that can learn from the environment and adapt to the change in the environment has been pursued by many researchers in this age of information technology. The Group Method of Data Handling (GMDH) algorithm to be implemented is a multilayered neural network. Neural network consists of neurons which use information acquired in training to deduce relationships in order to predict future responses. Most software tool during the simulation of the neural network based algorithms in a sequential, single processor machine like Pascal, C or C++ takes several hours or even days. But in this thesis, the GMDH algorithm was modified and implemented into a software tool written in Verilog HDL and tested with specific application (XOR) to make the simulation faster. The purpose of the development of this tool is also to keep it general enough so that it can have a wide range of uses, but robust enough that it can give accurate results for all of those uses. Most of the applications of neural networks are basically software simulations of the algorithms only but in this thesis the hardware design is also developed of the algorithm so that it can be easily implemented on hardware using Field Programmable Gate Array (FPGA) type devices. The design is small enough to require a minimum amount of memory, circuit space, and propagation delay.